This application claims the benefit of Korean Patent Application No. 2001-24685, filed May 7, 2001, the disclosure of which is hereby incorporated herein by reference in its entirety as if set forth fully herein.
The present invention relates to semiconductor devices, and more particularly, to semiconductor memory devices and related methods.
FIG. 1 is a diagram illustrating a conventional semiconductor memory cell connected to a write word line and a read word line. Referring to FIG. 1, the conventional semiconductor memory cell connected to a write word line AWWL1 and a read word line ARWL1 includes a latch circuit A120, a write circuit A140, a first read circuit A110, and a second read circuit A130.
The latch circuit A120 includes two PMOS transistors AP1 and AP2 and two NMOS transistors AN1 and AN2, thereby latching a predetermined external voltage applied to a first node AND1. The write circuit A140 transmits a predetermined voltage loaded in a write bit line AWBL1 to the first node AND1 of the latch circuit A120 in response to the write word line AWWL1.
The first read circuit A110 inverts the voltage level at the first node AND1 in response to the read word line ARWL1 and transmits the voltage to a read bit line ARBL1. The second read circuit A130 inverts the voltage level at a second node AND2 in response to the read word line ARWL1 and transmits the voltage to a complementary read bit line ARBLB1.
The conventional semiconductor memory device of FIG. 1 includes a plurality of semiconductor memory cells arranged in row and column directions.
FIG. 2 is a diagram illustrating a conventional semiconductor memory cell connected to a write word line and two read word lines. Referring to FIG. 2, the conventional semiconductor memory cell connected to a write word line AWWL1 and two read word lines ARWL1 and ARWL2 includes a latch circuit A220, a write circuit A240, a first read circuit A210, and a second read circuit A230.
The latch circuit A220 includes two PMOS transistors AP1 and AP2 and two NMOS transistors AN1 and AN2, thereby latching a predetermined external voltage applied to a first node AND1. The write circuit A240 transmits a predetermined voltage loaded in a write bit line AWBL1 to the first node AND1 of the latch circuit A220 in response to the write word line AWWL1.
The first read circuit A210 inverts the voltage level of the first node AND1 in response to a first read word line ARWL1 and/or a second read word line ARWL2 and transmits the voltage to a first read bit line ARBL1 and/or a second read bit line ARBL2. The second read circuit A230 inverts the voltage level of a second node AND2 in response to a first read word line ARWL1 and/or a second read word line ARWL2 and transmits the voltage to a first complementary read bit line ARBLB1 and/or a second complementary read bit line ARBLB2. The conventional semiconductor memory device of FIG. 2 includes a plurality of semiconductor memory cells arranged in row and column directions.
Referring to FIG. 1, the operation of the conventional semiconductor memory cell will be described. In a case where a logic high state xe2x80x9cHxe2x80x9d is recorded at the first node AND1 of the latch circuit A120, the write word line AWWL1 is controlled to activate the write circuit A140, the first node AND1 is charged with an electrical charge representing the state xe2x80x9cHxe2x80x9d of the write bit line AWBL1 through the write circuit A140.
In a case where a logic low state xe2x80x9cLxe2x80x9d is recorded at the first node AND1 of the latch circuit A120, the write word line AWWL1 is controlled to activate the write circuit A140, and an electrical charge stored in the first node AND1 is discharged into the write bit line AWBL1 through the activated write circuit A140.
The voltage level at the first node AND1 and/or the second node AND2 of the latch circuit A140 is output to an external device through the read bit line ARBL1 and the complementary read bit line ARBLB1 through the first read circuit A110 and/or the second read circuit A130.
Responsive to a signal of the read word line ARWL1, the first read circuit A110 inverts the voltage level at the first node AND1 and transmits the voltage level to the read bit line ARBL1. Since the read bit line ARBL1 is pre-charged to the state xe2x80x9cHxe2x80x9d, the voltage level of the read bit line ARBL1 is not changed if the voltage level at the first node AND1 is in the state xe2x80x9cHxe2x80x9d. However, if the voltage level at the first node AND1 is in the state xe2x80x9cLxe2x80x9d, an electrical charge of the read bit line ARBL1 is discharged into a supply voltage Vss through transistors AN5 and AN3 of the first read circuit A110, and thus, the first read bit line ARBL1 represents the state xe2x80x9cLxe2x80x9d.
The second read circuit A130 responding to a signal of the read word line ARWL1 inverts the voltage level at the second node AND2 and transmits the voltage to a first complementary read bit line ARBLB1. A method for inverting the voltage level of the second node AND2 and transmitting the voltage to the first complementary read bit line ARBLB1 is the same as a method for reading the voltage level at the first node AND1 by using the first read circuit A110.
The conventional semiconductor memory cells shown in FIGS. 1 and 2, however, may have disadvantages. If the first write word line AWWL1 is selected from a plurality of write word lines AWWL1 through AWWLN (not shown) and is in a state xe2x80x9cHxe2x80x9d, for example, a plurality of latch circuits A140 and A240, which are controlled by the first write word line AWWL1, are all activated. The voltage level of the write bit line AWBL1 should be applied only to the latch circuits A120 and A220 which are connected to one write circuit from the plurality of write circuits A140 and A240. However, charge re-distribution may occur even in the latch circuits A120 and A220 which are connected to the other write circuits. Thus, errors such as data being recorded in an unselected semiconductor memory cell may occur.
In a case where the read word lines ARWL1 and/or ARWL2 are in the state xe2x80x9cHxe2x80x9d during a read operation, one of the read bit line pairs ARBL1 and/or ARBL2 which has been already charged to the state xe2x80x9cHxe2x80x9d may be discharged regardless of the data stored in the latch circuits A120 and A220, resulting in unnecessary power consumption. This is a reason the first node AND1 and the second node AND2 have opposite voltage levels.
In addition, if charges of the second read bit line ARBL2 and the second complementary read bit line ARBLB2 are increased (see FIG. 2), assuming that the first read word line ARWL1 and the second read word line ARWL2 are simultaneously in the state xe2x80x9cHxe2x80x9d, an effective capacitance of a third node AND3, which is connected to both read bit lines ARBL1 and ARBL2, may increase, thereby increasing read time.
According to embodiments of the present invention, methods can be provided for reading data from a memory device comprising a plurality of memory cells and a plurality of virtual ground lines wherein each memory cell comprises a latch circuit coupled to a read circuit and wherein each virtual ground line is coupled with read circuits of a respective group of memory cells. Methods for reading according to embodiments of the present invention can include selecting a memory cell from which data is to be read, applying a first reference voltage to a virtual ground line coupled to the selected memory cell from which data is to be read, and applying a second reference voltage to a virtual ground line not coupled to the selected memory cell. A read word line coupled to the read circuit of the selected memory cell from which data is to be read can be activated. Responsive to activating the read word line coupled to the read circuit of the selected memory cell from which data is to be read, data can be coupled from the latch circuit of the selected memory cell with a respective read bit line through the read circuit of the selected memory cell.
According to additional embodiments according to the present invention, methods can be provided for writing data to a memory device comprising a plurality of memory cells, wherein each memory cell comprises a latch circuit having first and second complementary latch outputs and first and second write circuits respectively coupled to said first and second latch outputs. Methods for writing according to embodiments of the present invention can include selecting a memory cell to which data is to be written, activating a write word line coupled to the first and second write circuits of the selected memory cell to which data is to be written, and applying complementary write values to complementary write bit lines of a write bit line pair coupled with the first and second write circuits of the selected memory cell. Responsive to activating the write word line coupled to the first and second write circuits of the selected memory cell to which data is to be written, the first and second latch outputs of the selected memory cell can be coupled with the complementary write bit lines of the write bit line pair coupled therewith to write the complementary write values to the first and second latch outputs of the selected memory cell.